The present invention relates generally to testing of integrated circuits, and more specifically to a method and apparatus that reduces the time and testing resources needed for testing of memory integrated circuits.
Integrated circuits are extensively tested both during and after production, and, in some cases, routinely during use after they have been installed in products. For example, memory devices, such as dynamic random access memories (xe2x80x9cDRAMsxe2x80x9d), are tested during production at the wafer level and after packaging, and they are also routinely tested each time a computer system using the DRAMs executes a power-up or xe2x80x9cbootxe2x80x9d routine when power is initially applied to the computer system. As the capacity of DRAMs and other memory devices continues to increase, the time require to test the DRAMs continues to increase, even though memory access times continue to decrease.
A typical RAM integrated circuit includes at least one array of memory cells arranged in rows and columns. Each memory cell must be tested to ensure that it is operating properly. In a typical prior art test method, data having a first binary value (e.g., a xe2x80x9c1xe2x80x9d) are written to and read from all memory cells in the arrays, and thereafter data having a second binary value (e.g., a xe2x80x9c0xe2x80x9d) are typically written to and read from the memory cells. A memory cell is determined to be defective when the date that is read from the memory cell does not equal the data that was written to the memory cell. As understood by one skilled in the art, other test data patterns may be utilized in testing the memory cells, such as an alternating bit pattern, e.g., 101010 . . . , written to the memory cells in each row of the arrays.
One situation requiring testing of memory integrated circuits occurs during fabrication of memory integrated circuits. Fabrication yields are reduced when fabrication errors occur. Testing of memory integrated circuits during fabrication allows the sources of some fabrication errors to be promptly identified and corrected.
Another situation requiring testing of integrated circuits also occurs in fabrication of memory integrated circuits. Defective memory cells are identified by testing and are replaced with non-defective memory cells from a set of spare or redundant memory cells. In one conventional method for replacing defective memory cells, fuses on the integrated circuit are blown in a pattern corresponding to the addresses of defective memory cells. The pattern is then read to select redundant memory cells to replace the defective memory cells.
FIG. 1 is a simplified block diagram of several integrated circuit memory devices 10 and an automated tester 12 according to the prior art. Separate buses 14 couple each of the memory devices 10 on a circuit board 16 to the automated tester 12 through a connector 18. The buses 14 convey stimuli, such as write data, from the automated tester 12 to the memory devices 10 that are being tested. Transmission of the write data to the memory devices 10 does not require separate buses 14 because the same data are typically written to all of the memory devices 10.
Each memory device 10 generates a response, such as read data, from the data that are written to that memory device 10. The buses 14 convey the read data from each memory device 10 back to the automated tester 12. The automated tester 12 compares the read data from each memory device 10 to expect data, which correspond to the write data. The expect data thus correspond to read data that would be provided by the memory device 10 if it was operating properly. When the read data and the corresponding expect data match, the memory device 10 is considered to be functioning normally. When the read data do not match the corresponding expect data, the memory device 10 is considered to be malfunctioning.
If the memory devices 10 are read at the same time. transmission of the read data from the memory devices 10 requires separate buses 14 because read data resulting from failures in one or more of the memory devices will differ from each other. When these differing read data are transmitted over a common bus, contention between the differing data results in ambiguity as to which memory device 10 provided the read data corresponding to the defective memory cell and may also result in ambiguity in determining the data that are present on the bus 14. The automated tester 12 must therefore read data from each of the memory devices 10 individually. As a result, reading data from the memory device 10 requires more time than does writing to the memory devices 10. The requirement that data be read from each memory device 10 individually results in relatively long test times. Yet test time is a significant cost factor for manufacturers of memory devices 10. Additionally, since longer tests increase the number of automatic testers required to test a given number of memory devices 10, the cost of testing in further increased, particularly since automated testers 12 may cost several million dollars apiece.
Testing times may be minimized by testing multiple memory devices 10 at the same time. However, each automated tester 12 can only accommodate a finite number of buses 14, thereby limiting the number of memory devices 10 that may be simultaneously tested. The number of memory devices 10 that may be simultaneously coupled to the automated tester 12 is known as the xe2x80x9cfanoutxe2x80x9d for the automated tester 12. One factor limiting fanout for each automated tester 12 involves the connector 18 that couples the circuit board 16 holding the memory devices 10. A practical upper limit for the number of pins on each connector 18 is about 300. Larger numbers of pins tend to result in connectors 18 that are not sufficiently reliable. As a result, the number M of memory devices 10 that can be simultaneously tested is limited to about 300/N, where N is the number of connections that an be made to each memory device 10. For example, an automated tester 12 having a capacity of about 300 data lines may be employed to simultaneously test, without data compression, two memory devices 10 having 128 bit wide data buses, or four memory devices 10 having 64 bit wide data buses. With data compression, the same automated tester 12 may test, for example, sixteen (or possibly even up to eighteen) memory sevices 10, but will only be able to receive 16 bits of read data from each memory device 10.
In any of these cases, the time required to analyze the read data obtained by testing the memory devices 10 often exceeds the time required to perform the tests. The time needed to analyze the test results may decrease when data compression is used, but the results of testing done using data compression may be ambiguous or may not be useful for some purposes. For example, testing using data compression may be incapable of identifying a specific faulty memory cell but instead may be capable of identifying only a group, e.g., a row or column, of memory cells containing the defective memory cell.
As a result, data compression tests tend to be xe2x80x9cgo/no-goxe2x80x9d tests for a given memory device 10 as a whole, rather than diagnostic tests providing detailed information (e.g., addresses) regarding specific defective memory cells. However, data compression tests may be used to replace groups of rows or columns when the compressed data show that at least one of the rows or columns in the memory array includes one or more defects.
While compressed data do not always support the repair operations described above, they are extremely useful for other test purposes because they greatly speed testing. These other test purposes include speed grading (i.e., determining the maximum clock frequency permitting reliable operation) of memory device 10.
In speed grading, the number of failures is relevant, and some inaccuracy in the measured number of failures may be quite acceptable. The number of failures measured in a test using read data compression is a lower bound for the total number of failures that occurred during the test because it is frequently impossible to determine from the compresses data when multiple failures result in a failure in the same compressed read bit location at the same time.
There are therefore needs to reduce the time required to test memory devices and to increase the fanout for automated testers.
In one aspect of the present invention, a test circuit for testing of multiple memory devices includes failure processors for collecting read data from memory devices that are being tested. The failure processor then compares the read data to corresponding expect data to provide failure data describing failures that have occurred in the memory devices that are being tested. The failure processors may store the failure data until an automated tester polls the failure processors to download the stored failure data. As a result, the amount of data flowing from the circuit board to the automated tester is reduced, decreasing the time required to test the memory devices.
In another aspect of the invention, the failure processor also includes capabilities for analyzing the failure data to provide a post-analysis dataset that is much more compact than either the test data or the failure data. The failure data from many memory integrated circuits may be analyzed in real time by an ensemble of distributed failure processors, rather than by a central processor located in the automated tester. In one aspect of the invention, the automated tester sequentially polls the failure processors to download post-analysis datasets. Downloading post-analysis datasets requires substantially less time than downloading test or failure data because the post-analysis dataset is more compact than either the test or the failure data.
Testing of memory integrated circuits is thereby facilitated, reducing the time required for testing memory devices and increasing the fanout from automated testers.